The present disclosure relates to a method of forming interconnects for semiconductor devices.
Increases in the speeds of complementary metal oxide semiconductor (CMOS) logic devices may have typically depended on reducing gate delay times, based on reductions in gate length. Currently, however, as semiconductor devices have become highly integrated, the speed of devices may have come to depend largely on a resistance capacitance (RC) delay caused by metal wires formed, for example, in back end of line (BEOL). In order to reduce the RC delay, copper having a specific resistance lower than that of aluminum, and having more better resistance to electro-migration and stress directed migration characteristics than that of aluminum, has been used as a metal interconnect material. Such copper is not easily etched, and thus, in order to precisely form a copper interconnect, misalignment of an interconnect process should be reduced.